1. Field of the Invention
The present invention relates to a semiconductor device and to a method of fabricating a semiconductor device. More particularly, the present invention relates to a semiconductor device having capacitors and to a method of fabricating capacitors of a semiconductor device.
2. Description of the Related Art
To meet the current demand for more compact electronics, the degree to which semiconductor devices, such as dynamic random access memories (DRAMs), are integrated is being increased so that the resulting semiconductor devices occupy smaller areas. However, the capacitance of a cell of a semiconductor device must be increased or, at a minimum, maintained, if the device is to minitiarized. Generally, techniques used to obtain sufficient cell capacitance within a limited area include a technique of forming a dielectric layer of the cell capacitor from a high-k dielectric material, techniques aimed at minimizing the thickness of the dielectric layer, and techniques aimed at maximizing the effective area of a lower electrode of the cell capacitor. The forming of a high-k dielectric layer requires dedicated processing equipment. Also, the reliability and productivity of the process of forming a high-k dielectric layer must be subsequently verified through additional processes. Furthermore, the fabrication processes which follow must be carried out at lower temperatures than normal. Thus, adopting this technique incurs costs associated with investing in new equipment, and costs associated with the long amount of time it takes to fabricate the devices. Therefore, techniques aimed at maximizing the effective area of the lower electrode of the cell capacitor have been more widely employed in developing new generations of semiconductor devices because they allow the dielectric layer to be fabricated in the same way as in the older generation devices.
Forming the lower electrode in the shape of a cylinder or pin, growing hemispherical grains (HSG) on the lower electrode, and maximizing the height of the lower electrode have all been used to increase the effective area of the lower electrode. However, it is difficult to obtain the desired critical dimension between lower electrodes formed by growing HSGs. Furthermore, the HSGs can delaminate. Therefore, when fabricating a semiconductor device having a design rule less than 0.14 μm, a bridge is likely to form between the lower electrodes. Therefore, the most widely used techniques for forming capacitors of semiconductor devices are those which form the lower electrodes of the capacitors in the shapes of solids and those which aim to maximize the height of the lower electrodes. In particular, techniques of forming the lower electrode in the shape of a cylinder or as a stack have been widely used to fabricate capacitors of semiconductor devices.
The effective area of a capacitor lower electrode, formed in the shape of a cylinder or as a stack, corresponds to the area of the outer surface of the electrode or the sum of the areas of the inner and outer surfaces of the electrode. Therefore, the effective area of such lower electrodes can be increased by making the structure of the lower electrodes taller. In this respect, attempts have been made to increase the height of a lower electrode having an integrated one-cylinder-stack (OCS) structure. However, tail lower electrodes having an integrated one-cylinder-stack (OCS) structure frequently collapse or are damaged before a dielectric layer of the capacitor is deposited thereon. The collapse or damage of the lower electrode is often caused by surface tension exerted on the lower electrode by a cleaning solution when the cleaning solution dries. The cleaning solution is used to clean the lower electrode after a mold layer, used to form the lower electrode, is wet-etched.